1. Field of the Invention
The present invention relates to a solid-state imaging device which is applicable to camera systems such as video cameras, monitor cameras, door checker cameras, on-vehicle cameras, cameras for TV telephone and cameras for multimedia, and a method for driving the same. In particular, the present invention relates to a solid-state imaging device which contributes to the reduction of voltage and power consumption of a camera system, and a method for driving the same.
2. Description of the Related Art
FIG. 4 shows the structure of a conventional solid-state imaging device. As shown in FIG. 4, the solid-state imaging device includes a plurality of photoelectric conversion elements 110 arranged in a matrix, a plurality of vertical transfer sections 130, and a horizontal transfer section 140. The photoelectric conversion elements 110 act as light receiving elements. Each of the vertical transfer sections 130 is composed of a charge-coupled device (hereinafter, referred to as CCD) disposed along a column of the photoelectric conversion elements 110. The horizontal transfer section 140 is disposed at the bottom ends of the vertical transfer sections 130.
Signal charges stored in the photoelectric conversion elements 110 are transferred to the vertical transfer sections 130 once every field period. The vertical transfer sections 130 then sequentially transfer the injected signal charges in a vertical direction (i.e., in a direction in which the vertical transfer sections 130 elongate) before the start of the next field period. The horizontal transfer section 140 receives the signal charges output sequentially from the vertical transfer sections 130 and transfers the signal charges horizontally in series.
The signal charges transferred from the horizontal transfer section 140 are output as signal outputs by a signal output circuit. FIG. 5 schematically shows the configuration of the conventional signal output circuit.
The signal output circuit shown in FIG. 5 includes a reset circuit 1, a floating diode 2, and an amplification circuit 3. The reset circuit 1 applies a reset voltage Vr of about 15 V to the floating diode 2 prior to the detection of charges, so that a terminal voltage of the floating diode 2 is set at the reset voltage Vr. Thereafter, the charges transferred from the horizontal transfer section 140 are accumulated in the floating diode 2. As a result, the terminal voltage of the floating diode 2 changes. The amplification circuit 3 receives the terminal voltage of the floating diode 2, and outputs a signal in accordance with the change in voltage. Thereafter, the reset circuit 1 reapplies the reset voltage Vr to the floating diode 2, so that the charges transferred from the horizontal transfer section 140 are transferred to the floating diode 2 again.
The floating diode 2 includes a semiconductor substrate and a diffusion layer N.sup.+ which is in a potentially floating state formed on the semiconductor substrate. The diffusion layer N.sup.+ and a P-well of the semiconductor layer formes a PN junction, thereby forming a diode. The diode also serves as a capacitor.
A change in voltage Vq of the floating diode 2 is expressed by the following Expression 1: EQU Vq=Q/C [Expression 1]
where C is a capacitance of the floating diode 2, and Q is the amount of charges transferred from the horizontal transfer section 140 to the floating diode 2.
Since the floating diode 2 has a remarkably high output impedance, it is not possible to output signals. Therefore, in order to lower the output impedance, a plurality of source follower circuits 4 and 5 are provided in parallel for the amplification circuit 3. A signal corresponding to a change in voltage Vq is output through the source follower circuits 4 and 5.
A constant current source 8 is connected to a source of a transistor 6 of the source follower circuit 4, while a constant current source 9 is connected to a source of a transistor 7 of the source follower circuit 5. Each of the constant current sources 8 and 9 is constituted by a transistor.
The reason that a plurality of source follower circuits are provided in parallel is as follows.
First, an output impedance R.sub.out of the source follower circuit is expressed by Expression 2 below: EQU R.sub.out .varies.[(W/L).times.I].sup.-1/2 [Expression 2]
where W is a gate width of a transistor of the source follower circuit, L is a gate length thereof, and I is a current flowing from the drain to the source.
As is apparent from Expression 2, the output impedance R.sub.out of the source follower circuit can be lowered by increasing a value of (W/L).times.I.
However, if the gate width W is increased, the capacitance C of the floating diode 2 in Expression 1 above is accordingly increased. Since a change in voltage Vq is reduced thereby, increasing the gate width W is not desirable for lowering the output impedance of the source follower circuit. In fact, the gate width W should be made as small as possible so that the transistor does not suffer from the effects of noise or the like.
In order to lower the output impedance R.sub.out, it may be possible to reduce the gate length L or increase the current I. However, the reduction of the gate length L or the increase of the current I is limited by noise effects.
Even if the source follower circuit is employed, it is not possible to sufficiently reduce the output impedance R.sub.out with a single source follower circuit. Therefore, a plurality of source follower circuits are provided in parallel, so the output impedance is gradually reduced by passing the input signal through the plurality of source follower circuits.
Specifically, a plurality of source follower circuits are designed so that the value of (W/L).times.I increases by passing the input signal through the source follower circuits to reduce the output impedance. In accordance with such a configuration, the last source follower circuit requires a current of 3 to 4 mA or more.
For example, Japanese Laid-Open Publication Nos. 3-274811, 5-251677, and 6-70239 disclose such a solid-state imaging device employing a plurality of source follower circuits.
In the case where the plurality of source follower circuits 4 and 5 are employed, it is preferred to set a power supply voltage at a high level. The reason for this is as follows. A DC current voltage level is lowered as it flows from the input to the output of the source follower circuit. If the current voltage drops below a certain voltage (that is, the lower limit voltage below which the constant current sources 8 and 9 constituted by transistors do not operate), the source follower circuits 4 and 5 do not operate. The range of the DC voltage level allowing the source follower circuits to operate is increased at a higher power supply voltage. Therefore, setting a power supply voltage at a high level is advantageous in terms of dynamic range.
In order to preserve such a high power supply voltage Vod1, a relatively high reset voltage Vr, that is, 15 V on the floating diode 2 as described above, is used. As a result of this, the system can be simplified.
However, in the case where the power supply voltage Vod1 is set at a high value, the power consumption is disadvantageously increased because the current passing through the source follower circuits is increased in order to lower the output impedance R.sub.out of the source follower circuits.